Electrical Engineering internship: remote jtag access over ethernet

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ASML offers a six-month hybrid electrical engineering internship focused on remote JTAG access over Ethernet, based in Veldhoven with a start in September 2026. You will join the Generic Design Blocks team within Motion Control to build reusable FPGA modules and enable networked debugging and programming, reducing the need for physical access. Your work spans designing an Ethernet access solution for FPGA debug interfaces, developing a host interface, implementing an embedded server, ensuring reliable host-target data exchange, and validating the system on Windows and Linux while documenting for reuse. To apply effectively, highlight FPGA concepts, C or C++ experience, independent problem solving and teamwork, confirm eligibility for controlled technology, and mention any on-site preference.

Introduction

The Generic Design Blocks team is part of the Motion Control cluster at ASML. You will work in a group that builds reusable FPGA design modules used across advanced lithography systems. This internship focuses on enabling remote access to FPGA debug interfaces. Your work will help engineers collaborate more efficiently and reduce development time. As part of this internship, you will contribute to a practical solution with real impact on engineering workflows.

Your assignment

In this internship, you will design and implement a system that enables remo FPGA programming and debugging over a network. The goal is to replace physical access with a flexible remote solution that works on multiple operating systems. Your work will support typical FPGA development workflows and improve accessibility for engineers worldwide. Your main responsibilities will be:

• Design a solution to access FPGA debug interfaces over Ethernet

• Develop a host-side interface compatible with FPGA development software

• Implement an embedded server to control FPGA communication signals

• Enable reliable data exchange between host system and embedded target

• Test the system across Windows and Linux environments

• Validate functionality with programming and debug use cases

• Document the solution for future reuse and scaling

This is a bachelor/masters thesis/non-thesis internship for 6 months, 5 days per week (3 days on-site). The start date of this internship is as of September 2026.

Your profile

To be suitable for the internship, you:

• Are studying for a bachelor’s degree in electrical engineering, embedded systems, or software engineering

• Have basic knowledge of FPGA concepts and digital design

• Have experience with programming in C, C++, or similar languages

• Are analytical and able to solve technical problems independently

• Communicate clearly and collaborate effectively with others

This position requires access to controlled technology, as defined in the United States Export Administration Regulations (15 C.F.R. § 730, et seq.). Qualified candidates must be legally authorized to access such controlled technology prior to beginning work. Business demands may require ASML to proceed with candidates who are immediately eligible to access controlled technology.

Inclusion and diversity

ASML is an Equal Opportunity Employer that values and respects the importance of a diverse and inclusive workforce. It is the policy of the company to recruit, hire, train and promote persons in all job titles without regard to race, color, religion, sex, age, national origin, veteran status, disability, sexual orientation, or gender identity. We recognize that inclusion and diversity is a driving force in the success of our company.

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