DRW seeks a Senior FPGA Engineer to join trading teams in London, Chicago, or NYC to deliver high‑throughput, low‑latency FPGA solutions from requirements through production. Responsibilities include architecting and implementing FPGA applications, handling synthesis, place and route, static timing analysis, and documentation, plus lab debugging and hardware characterization while collaborating with software and other design teams. The ideal candidate has 3+ years in FPGA hardware, solid RTL Verilog, experience with SOC architectures and memory or networking subsystems, TCP/IP, and toolchains for either Xilinx or Altera. To apply, tailor your resume to end‑to‑end project leadership, quantify latency and throughput improvements, showcase collaboration and lab work, and demonstrate autonomy and integrity.
DRW is a diversified trading firm with over 3 decades of experience bringing sophisticated technology and exceptional people together to operate in markets around the world. We value autonomy and the ability to quickly pivot to capture opportunities, so we operate using our own capital and trading at our own risk.
Headquartered in Chicago with offices throughout the U.S., Canada, Europe, and Asia, we trade a variety of asset classes including Fixed Income, ETFs, Equities, FX, Commodities and Energy across all major global markets. We have also leveraged our expertise and technology to expand into three non-traditional strategies: real estate, venture capital and cryptoassets.
We operate with respect, curiosity and open minds. The people who thrive here share our belief that it’s not just what we do that matters–it's how we do it. DRW is a place of high expectations, integrity, innovation and a willingness to challenge consensus.
We are currently seeking a Senior FPGA Engineer to join one of our trading teams in Chicago, NYC, or London. While DRW has been leveraging FPGA technology for a number of years, you will have the opportunity to build FPGA applications for existing teams. We’re seeking a candidate that has a strong understanding of software and hardware interaction. This person will participate in the full development lifecycle, including system and block level testing, of low latency high throughput FPGA design.
Responsibilities:
Candidate Requirements: