Technical Lead Digital Design Engineer

JobsCloseBy Editorial Insights

Astera Labs is seeking a Technical Lead Digital Design Engineer in Toronto for full-time onsite. The role centers on high‑performance PCIe controller and Serdes/PHY IP design, RTL implementation, and IP integration, guiding block‑level to full‑chip work through 16nm nodes with timing closure and verification across front‑end, back‑end, and pre/post‑silicon stages. You’ll use Synopsys Cadence tools, own architecture to GDS, and collaborate with cross‑functional teams. Basic qualifications include a BS in electronics/EE, 5+ years in digital design with PCIe/PCS/PHY, SystemVerilog, Python/Perl, and experience with timing closure, CDC, and lint. Preferred: PCIe SerDes IP, DFT, floor planning, embedded FW, CI/CD. Diversity encouraged.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.

Job Description

We are seeking a Technical Lead Digital Design Engineer with deep expertise in high-performance PCIE controller and bridge design, micro-architecture, RTL implementation, and IP integration. The ideal candidate will play a critical role in the development of cutting-edge connectivity solutions.

Key Responsibilities:

• Design and implement high-performance digital solutions, including RTL development and synthesis.
• Collaborate with cross-functional teams on IP integration for Serdes and Controller IPS, processor and peripherals
• Own block-level and full-chip designs from architecture to GDS, focusing on designs at nodes ≤ 16nm.
• Ensure timing closure, assess verification completeness, CDC, lint etc.
• Utilize tools from Synopsys/Cadence for design and emulation.

Basic Qualifications:

• Bachelor’s in Electronics/Electrical engineering (Master's preferred).
• 5+ years of digital design experience, with 4+ years focused on PCIE controller, PCS or PHY implementation.
• Proven expertise in RTL development, synthesis, and timing closure.
• Experience with front-end design, gate-level simulations, and design verification.
• Strong work ethic, ability to handle multiple tasks, and a proactive, customer-focused attitude.

Required Expertise:

• Hands-on experience with PCIE Controller or Serdes/PHY IP.
• Hands-on pre-silicon and post-silicon design implementation.
• Hands-on experience  FW interaction and embedded design.
• Strong proficiency in System Verilog/Verilog and scripting (Python/Perl).
• Experience with block-level and full-chip design at advanced nodes (≤ 16nm).
• Top level integration and DFT knowledge.

Preferred Experience:

• PCIE SerDes controller or IP level experience.
• Understanding of PAD design, DFT, and floor planning.
• Experience with NIC, switch, or storage product development including embedded FW.
• Familiarity with working in design and verification workflows in a CI/CD environment.

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.