Engineer, PCB Layout Design, meoSphere

JobsCloseBy Editorial Insights

SES seeks an energetic PCB Layout Design Engineer to drive the design and optimization of satellite payloads, with expertise in high speed digital and RF PCB design up to 30 GHz, including stackups, PDN and manufacturing constraints. You will collaborate with electrical and mechanical engineers, fabrication houses, procurement in a team to ensure mission success. Qualifications include a BS or MS in EE or Physics, 2+ years PCB layout, Altium Designer (365/Agile), PAM4 and DDR4 experience, and solid knowledge of transmission line theory and RF layout. On-site 60 percent, travel, and SECRET clearance eligibility. To apply, highlight controlled impedance RF routing, high speed interfaces, via management, and collaboration, problem solving and first principles thinking; mention NewSpace exposure if applicable.

The job responsibilities outlined in this document are not exhaustive and may evolve over time and be reviewed according to business needs.

ROLE DESCRIPTION SUMMARY

We are seeking a highly energetic PCB Layout Design Engineer to play a central role in the design and optimisation of advanced satellite payloads. This position requires expertise in high speed digital, and sensitive RF PCB design including stackup definition, technology selection, part reliability knowledge and PCB/PCBA manufacturing for signals up to 30GHz. 

As part of an agile, international team, you will work closely with electrical, mechanical engineers, PCB manufacturing houses, procurement and manufacturing counterparts to ensure mission success. Adaptability, strong collaboration skills, and a problem-solving mindset are essential to thrive in this role. 

PRIMARY RESPONSIBILITIES / KEY RESULT AREAS

PCB Design 

• Implement controlled‑impedance RF transmission lines (microstrip, stripline, CPWG) with precise geometry and dielectric modelling. 
• Optimize RF path length, symmetry, and isolation to minimize loss, reflections, and phase imbalance 
• Integrate antennas (chip, PCB trace, patch, loop) with proper clearance, ground tuning, and keep‑out zones 
• Collaborate with other engineers to validate S‑parameters, insertion loss, and return loss 
• Generate fabrication notes for RF stackups, materials and tolerances 
• Route high‑speed interfaces (PCIe, DDRx, RFFE, 112G SERDES) 
• Manage via transitions (back‑drilling, blind/buried vias, via‑in‑pad) to reduce reflections and stubs 
• Design power distribution networks (PDN) with guidance 

Qualifications & Compentencies

• Bachelor’s or Master’s degree in Electrical Engineering, or Physics. 
• 2+ years of experience in PCB layout design. 
• Experience with Altium Designer (preferably Altium 365/Agile) 

• Experience with high speed PAM4 signalling 

• Experience with DDR4 or other high speed parallel buses where timing is critical 

• First principles thinking  

• Experience with manufacturing technologies and bottlenecks (lamination cycles, copper types, dielectric types and uses) 

• Understanding of Power Delivery Networks and transmission line theory 

• Experience with RF layout considerations 

• Nice to have: Experience with NewSpace development approaches. 

• Fluency in English; other languages are considered an asset. 

OTHER KEY REQUIREMENTS / COMMENTS

• The candidate must be eligible for a “SECRET” security clearance, in accordance with the national regulations as well as EU/ESA/NATO equivalents
• Willing to work at least 60% onsite from office
• Travel as required for project realization purposes 

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