Stage Ingénieur : Application de l'Intelligence Artificielle à l'intégration de blocs RTL (ASIC/FPGA) (H/F)

NXP Semiconductors is looking for a final-year engineering student for a six-month, on-site internship in Valbonne, France. The role sits in the Digital HW/SoC team within the Secure Connected Edge unit and aims to build AI-based methods to assist the integration of RTL IP blocks for ASIC and FPGA projects. You’ll join a team that serves markets like mobile communications, secure payments, digital identity, IoT, and NFC, and you’ll see the full hardware development cycle, from specification and architecture through verification and validation, up close. If you enjoy hands-on digital design challenges and collaborating with colleagues across sites, this can be a strong match.

The internship is designed for someone in the last year of their engineering studies or master’s program, and it operates in an international environment where English is the working language. You’ll contribute to designing and testing AI-assisted tools that help engineers automate and improve the reliability of RTL IP integration, with the goal of reducing errors and speeding up workflows in ASIC and FPGA projects.

Daily rhythm in RTL integration with AI

Your days will balance learning and doing. You’ll begin by getting up to speed on the team’s existing RTL integration and verification flows and by exploring NXP’s internal AI platform. As you gain familiarity with the IP landscape, you’ll pinpoint common pain points and recurring mistakes that happen when IP blocks are combined, then start implementing AI-enabled analyses to address these gaps. You’ll work toward automatically extracting RTL parameters, recognizing standard interfaces, spotting polarity issues, and flagging typical integration problems such as clock and reset connections or port mappings. The aim is to weave these analyses into the current design and verification flow and to produce practical reports for design teams.

Across the project, you’ll contribute to the development of a prototype integration-assistance tool, which could take the form of scripts, a graphical interface, or a plugin. You’ll integrate AI-driven insights into established RTL design and verification workflows and generate reports that engineering teams can act on. Finally, you’ll participate in validating the solution on a representative set of real IPs and compare the results to traditional manual methods to quantify improvements in time, quality and error detection.

Your must-have foundations

• Solid experience with digital RTL design and a working knowledge of Verilog, SystemVerilog or VHDL

• Software development and scripting skills, with Python or Perl as a preferred path

• Comfortable working in a Linux environment

Nice-to-have capabilities

• Familiarity with hardware protocols such as AXI, APB, or AHB

• Experience with ASIC/FPGA simulation and synthesis tools

• Exposure to applying artificial intelligence to engineering or design automation

Pay, benefits and practical details

The opportunity runs six months and is performed on site in Valbonne, France, within an international, multisite setting. The internship is positioned as a full-time assignment, and English is required to collaborate effectively with colleagues across sites. No further compensation details are disclosed in the description.

If you’d like to learn more about NXP’s presence in France, you can explore this page: More information about NXP in France...

A thoughtful tip for prospective applicants: tailor your resume to front-load RTL design and scripting competencies, showcase a relevant project that involved RTL/IP integration, and highlight your experience with Linux and at least one scripting language.

Another practical note: be ready to discuss a concrete IP integration challenge you tackled, including how you used tools and processes to identify issues and what the outcome was. If you can point to an example where you automated a part of the workflow, you’ll stand out.

During the interview, expect questions about how you would approach detecting interface or polarity problems and how you would validate an AI-assisted analysis against traditional methods. It’s also smart to prepare a question about the AI platform’s current capabilities and where the team sees opportunities for industrial deployment.